High Performance Computing: Programming and Applications presents techniques that address new performance issues in the programming of high performance computing (HPC) applications. Omitting tedious details the book discusses hardware architecture concepts and programming techniques that are the most pertinent to application developers for achieving high performance. Even though the text concentrates on C and Fortran the techniques described can be applied to other languages such as C++ and Java. Drawing on their experience with chips from AMD and systems interconnects and software from Cray Inc. the authors explore the problems that create bottlenecks in attaining good performance. They cover techniques that pertain to each of the three levels of parallelism: Message passing between the nodes Shared memory parallelism on the nodes or the multiple instruction multiple data (MIMD) units on the accelerator Vectorization on the inner level After discussing architectural and software challenges the book outlines a strategy for porting and optimizing an existing application to a large massively parallel processor (MPP) system. With a look toward the future it also introduces the use of general purpose graphics processing units (GPGPUs) for carrying out HPC computations. A companion website at www. hybridmulticoreoptimization. com contains all the examples from the book along with updated timing results on the latest released processors. | High Performance Computing Programming and Applications
High Performance Computing: Programming and Applications presents techniques that address new performance issues in the programming of high performance computing (HPC) applications. Omitting tedious details the book discusses hardware architecture concepts and programming techniques that are the most pertinent to application developers for achieving high performance. Even though the text concentrates on C and Fortran the techniques described can be applied to other languages such as C++ and Java. Drawing on their experience with chips from AMD and systems interconnects and software from Cray Inc. the authors explore the problems that create bottlenecks in attaining good performance. They cover techniques that pertain to each of the three levels of parallelism: Message passing between the nodes Shared memory parallelism on the nodes or the multiple instruction multiple data (MIMD) units on the accelerator Vectorization on the inner level After discussing architectural and software challenges the book outlines a strategy for porting and optimizing an existing application to a large massively parallel processor (MPP) system. With a look toward the future it also introduces the use of general purpose graphics processing units (GPGPUs) for carrying out HPC computations. A companion website at www. hybridmulticoreoptimization. com contains all the examples from the book along with updated timing results on the latest released processors. | High Performance Computing Programming and Applications
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